The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, when fabricating field effect transistors (FETs), such as fin-like FETs (FinFETs), device performance can be improved by using a metal gate electrode instead of a typically polysilicon gate electrode. One process of forming a metal gate stack is termed a replacement-gate or “gate-last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that is performed after formation of the gate. However, there are challenges to implementing such IC fabrication processes, especially with scaled down IC features and complex surface topology in advanced process nodes, such as N16, N10, and beyond. One challenge is that metal patterning processes may damage metal barrier layers provided between the metal gate electrode and a gate dielectric layer. Consequently, metal materials may intrude into the gate dielectric layer, causing device defects.